Moore's law isn't dying of neglect. It's dying of physics. For fifty years the semiconductor industry delivered exponential performance gains by shrinking transistors, a strategy so reliable it became an economic constant. But the atoms are running out of room, and the demand side isn't slowing down.

AI training compute has been doubling every five to six months since 2020. Global data-center electricity consumption hit roughly 460 TWh in 2022, and the IEA projects it will exceed 1,000 TWh by 2026, equivalent to Japan's entire national grid. The semiconductor market crossed $630 billion in 2024 and is on track toward $1 trillion by decade's end. Every dollar of that growth assumes the industry can keep making transistors faster, cheaper, and more power-efficient.

The question is whether silicon can keep delivering.

What breaks at the sub-3 nm node

Dennard scaling (the observation that as transistors shrink, their power density stays constant) ended around 2005. Since then the industry has bought time with architectural innovations: FinFETs in 2011, gate-all-around nanosheets in 2022, complementary FETs on the horizon. Each buys another half-generation of scaling. None of them solve the underlying material limit.

The problems at sub-3 nm are fundamental:

• Quantum tunneling through gate oxides. At ~1 nm oxide thickness, electrons tunnel directly through the insulator. Leakage current grows exponentially. No amount of clever geometry fixes this; it's a property of the wavefunction.
• Short-channel effects. When the gate length approaches the depletion width, the gate loses electrostatic control of the channel and the transistor stops switching cleanly.
• Surface scattering. In a silicon channel thinner than ~5 nm, carriers scatter off the top and bottom interfaces. Effective mobility degrades rapidly. You're fighting the crystal surface, not benefiting from the bulk.
• Interconnect RC delay. Copper lines at sub-20 nm pitch hit resistivity walls due to grain-boundary and surface scattering. The wires connecting transistors become the bottleneck, not the transistors themselves.
• Thermal density. Power per unit area continues to rise even as supply voltage plateaus. Removing heat from a 3D-stacked chiplet at over 100 W/cm² is an unsolved packaging problem.

These aren't engineering challenges that yield to more R&D spending on the same material system. They're intrinsic to silicon at these dimensions.

Silicon's atomic floor

The core tension: a silicon channel can't be thinned below about 3-5 nm and still function as a useful semiconductor. Below that thickness, quantum confinement collapses the bandgap, surface states dominate transport, and mobility falls off a cliff. The material itself stops behaving like silicon.

Transition metal dichalcogenides (MoS₂, WSe₂, WS₂) don't have this problem. A monolayer of MoS₂ is 0.65 nm thick by construction. It's a single unit cell. There is no thinner version, and it retains a direct bandgap of ~1.8 eV, useful on/off ratios exceeding 10⁸, and immunity to short-channel effects at gate lengths where silicon has already failed.

This is a qualitative change in what is physically possible, not a marginal improvement.

Mobility values reflect state-of-the-art device demonstrations as of 2024. TMD mobilities are improving year-over-year with better contacts and dielectric interfaces. Sources: Akinwande et al., Nature 573, 507 (2019); Benchmarking MoS₂ and WS₂ FETs, Nat. Commun. (2021); IMEC 2D-material device results (2025).

The mobility gap is real. Silicon in bulk is still a better conductor. But at sub-5 nm channel thickness, silicon's effective mobility degrades to the point where monolayer TMDs are competitive or superior. And TMDs bring something silicon never will at these dimensions: perfect electrostatic control from a gate wrapping a body that is genuinely one atom thick.

The four levers

Replacing the channel material is only one of the things 2D materials enable. The same family of atomically thin crystals addresses at least four distinct bottlenecks in the post-silicon roadmap:

Sub-nanometer channels are the headline, the lever that shows up in IRDS roadmaps and IEDM papers from TSMC and IMEC. But the other three matter just as much for the system:

• Low-temperature 3D integration. TMDs can be deposited at ≤450 °C via MOCVD or ALD, which means you can grow a transistor layer on top of existing back-end-of-line metal without melting the copper interconnects below. That unlocks true monolithic 3D stacking (compute on top of memory on top of I/O), which is the only remaining geometric path to PPAC scaling once lateral shrinking stops.

• Low-κ dielectrics. Hexagonal boron nitride (hBN), another 2D material, has a dielectric constant of ~3-4 and can be grown as an atomically smooth insulator. At advanced nodes, the capacitive coupling between wires dominates dynamic power. Lower-κ insulators between those wires reduce crosstalk and RC delay, and hBN does this better than any amorphous oxide at equivalent thickness.

• Photonic interconnects. WSe₂ and MoSe₂ are direct-bandgap semiconductors that emit light efficiently at room temperature. Graphene makes an excellent broadband photodetector and modulator. Together they enable on-chip optical links that bypass the resistivity wall entirely for long-range data movement, whether chip-to-chip or across a large die.

No single material system since silicon has addressed this many bottlenecks at once. That's what makes 2D materials different from previous "beyond-silicon" candidates like III-V compounds or carbon nanotubes: they solve multiple problems simultaneously, at dimensions compatible with the fabs already in place.

The bottleneck has moved

If the device physics is becoming solvable, what's still hard? Materials science itself.

Growing a monolayer of MoS₂ that's uniform across a 300 mm wafer, with a defect density low enough for logic-grade devices, at a throughput compatible with volume manufacturing — that's where the problem lives now. IMEC's 2025 results on WSe₂ p-FETs demonstrate that the device performance is there. They also demonstrate that every step (nucleation control, grain-boundary engineering, transfer or direct growth, contact metallurgy) is still being optimized one experiment at a time.

Today's materials R&D cycle looks roughly like this: a team grows a film, characterizes it (often weeks later, with expensive TEM), correlates defects to process conditions by hand, adjusts one knob, and tries again. Iteration time is weeks to months. The number of experiments per year is dozens, not thousands.

That's the gap AI-driven materials platforms are designed to close. Simulation (MLIP-calibrated Raman fingerprinting, kinetic Monte Carlo growth models) can predict the outcome of a process change before the film is grown. In-situ spectroscopy can characterize the film in seconds, not days. Closed-loop control can iterate hundreds of recipe variations per week instead of a handful per quarter.

We wrote about what that closed loop looks like in practice in AI-native manufacturing for 2D materials. The short version: the bottleneck in semiconductor scaling has moved from device design to materials discovery and process control. Whoever solves the materials pipeline (simulation, synthesis, characterization, iteration) holds the key to the next decade of hardware progress.

The forcing function

AI created the demand that's now breaking silicon. It's also, almost certainly, the tool that will solve the materials problem replacing it.

The semiconductor industry has never faced a scaling wall it couldn't eventually engineer around. But for the first time, the answer isn't a new transistor geometry, a new lithography wavelength, or a new packaging trick. It's a new material — atomically thin, synthetically grown, computationally designed — placed at the exact point in the stack where silicon can no longer physically function.

2D materials are that answer. The physics is proven. The device results are published. The remaining question is how fast the materials science can move, and that's a question AI is exceptionally well-suited to accelerate.